The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
Traditionally, IC designers may utilize a set of design rules (for example design rules provided by a semiconductor fabrication foundry) to ensure that an IC design will fall within manufacturing tolerances. However, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density and higher performance, following design rules alone may not be able to ensure the successful fabrication of an IC. Lithography pattern check (LPC) simulations may also need to be performed on an IC design. LPC simulations allow IC designers and foundry personnel to see what effects the actual IC fabrication processes may have on eventual shapes of the various features on the IC. Therefore, accurate LPC simulations may allow IC designers to better predict the yield and performance of their ICs. However, conventional LPC simulations may not fully take into account of the topography variations on a semiconductor wafer surface.
Therefore, although existing LPC simulations have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.